A Mostly Digital PWM-Based ΔΣ ADC With an Inherently Matched Multibit Quantizer/DAC

A mostly-digital PWM-based delta-sigma (∆Σ) ADC is proposed. This system takes advantage of the duration of pulses, rather than voltage or current, as the analog operand used in its closed-loop operation. Therefore, circuits that process the pulses are digital in nature and improve with scaling. Furthermore, the architecture allows inherently matched multi-bit quantizer/DAC blocks by taking advantage of delay lines reusable in both quantization and DAC operation. A second novelty of this architecture is the modualtor’s adapative excess delay, that synchronizes the asynchronous loop with an external reference clock. This mitigates the problems associated with non-uniform sampling. A first order 3-bit prototype of this architecture is presented. The core occupies an area of 0.0275 mm in 0.18 μm CMOS process, consumes 2.7 mW, and measures 45.1 dB SNR over a 2 MHz bandwidth.